KEY FEATURE DEMONSTRATIONS Enter here to view special function demonstrations that show how easy our EDA software handles the most tedious tasks.

You will Flip Your Chip When You Bump Your Die with This.

Flip Chip / Die Bump automates the process of creating redistribution routing and bump artwork to convert a standard die to a flipchip die. The redistribution layer can be created easily and quickly directly on the IC through the use of our automated bump creation and interactive autorouting utilities. 

Direct GDS II read in ensures perfect alignment with the IC artwork. Die data may also be captured graphically or specified through parameters in a dialog box. Bumps can be created with our BallGrid command or another specialized bump pattern creator. Netlist data may be created interactively or automatically with flipchip-specific tools. Full netlist verification and DRC. Output can be made in Gerber and/or GDS II format.

Key Features Include:

1. GDSII stream file reader imports graphics from large dies and extracts relevant layers and entities by viewing a preview of the die's structure
   
   
2. BallGrid command makes patterns with a configurable number of levels and shapes for use as bumps
   
   
3. Automatic or interactive net list generation by 3 different methods
   
   
4. Autorouter designed for dense BGA routing with just enough clearance
   
   
5. Complete netlist verification and DRC
   
   
6. Wafer Array command panelizes the design in perfect alignment with the original silicon image
   
   

• Autorouter designed for dense BGA routing with just enough clearance

• Easy die creation tools can create dies by 6 different methods

  • Reads .LIQ files

  • Reads .DIE files

  • Reads .DWG files automatically

  • Reads GDSII Stream files to make .DWG files

  • Digital scans from photographs  with distortion compensation

  • Manual data entry into our DieMake dialog box

• Automatic orientation of die for redistribution on silicon design or for later substrate routing

• GDSII stream file reader imports graphics from large dies and extracts relevant layers and entities by viewing a preview of the die's structure

• Automatic or interactive net list generation by 3 different methods

• Wafer Array command panelizes the design in perfect alignment with the original silicon image

• Routing using automatic length tuning and matching

• Differential pairs are interactively  routed

• BallGrid command makes patterns with a configurable number of levels and shapes for use as bumps

• Complete netlist verification and DRC

• Ability to handle large designs (thousands of pins)

• GDSII stream file writer makes efficient files of entire panelized wafers